Centre Will Pour ₹4,500 Crore To Upgrade & Expand The Semiconductor Laboratory In Punjab
Union Electronics and Information Technology Minister Ashwini Vaishnaw announced on Friday that the Centre will invest Rs 4,500 crore to upgrade and expand the Semiconductor Laboratory (SCL), Mohali. The key vision areas include upgrading the facility on modern lines with a government investment of Rs 4,500 crore. This will include a large-scale increase in production capacity.

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Mohali (Punjab): Union Electronics and Information Technology Minister Ashwini Vaishnaw announced on Friday that the Centre will invest Rs 4,500 crore to upgrade and expand the Semiconductor Laboratory (SCL), Mohali. During his visit to Mohali, the minister said: "There is no doubt that SCL Mohali will be modernised and it will not be privatised. A big journey is ahead, and India is ready for it." Vaishnaw said that Prime Minister Narendra Modi has drawn a clear roadmap for SCL Mohali.
The key vision areas include upgrading the facility on modern lines with a government investment of Rs 4,500 crore. This will include a large-scale increase in production capacity, targeting 100 times the production of wafers from current levels. SCL Mohali will also continue to support students, researchers, and startups by providing fabrication facilities that turn their chip designs into real silicon. SCL will remain a platform for talent development, innovation and startups.
This fabrication support provided by SCL so far will further increase in future. To support the further modernisation programme of SCL, the Centre has also requested the Punjab government to allot 25 acres of land, Vaishnaw said at SCL Mohali during a programme where 28 chips designed by students from 17 academic institutions were handed over. These chips have been designed using Electronic Design Automation (EDA) tools provided to students as part of Chips to Start-up (C2S) programme.
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With this, a total of 56 chips designed by students have been fabricated at SCL as part of the programme. The minister also inaugurated the Semiconductor Process Gallery and Abhyuthanam Training Block. Semiconductor Process Gallery showcases a clean room lab equipped with earlier-generation fabrication tools. It offers students a real feel of a semiconductor fab and ATMP facility. The Abhyuthanam Training Block includes online and offline semiconductor training modules & hands-on fire and safety training.
Vaishnaw said that India is one of the few countries where students from nearly 300 universities are designing semiconductor chips using world-class EDA tools provided through government support. This ecosystem is unique in the world, he added. The minister added that self-reliance in strategic sectors is essential, and India will build an ecosystem for indigenous chip development. A strong consortium featuring the CDAC, the DRDO, and other organisations will work together on design, product development and manufacturing of swadeshi chips, he added.
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