Indore: Patience is essential for research and this is one of the most important lessons that we can learn in tough times like now, when we are fighting corona virus pandemic.
Discussing this, Shri Govindram Seksaria Institute of Technology and Science, Department of Electronics and Instrumentation Engineering inaugurated its six-days Online AICTE – STTP (Short Term Training Program) on ‘Mixed Signal and Radio Frequency VLSI Design’ from Monday.
“In current situation when we are not able to gather at one place to share knowledge, we have to find different platform to share and update our knowledge,” said college director Dr Rakesh Saxena.
He added that STTP aims to provide a platform for interaction with people of different knowledge domains, to update the faculty members and industry professionals about the current ongoing research in the field of Mixed Signal and Radio Frequency VLSI Design.
Various prominent speakers in VLSI domain from IIT, NIT, IIITM, research centres and Industries will share their knowledge on Mixed Signal and Radio Frequency VLSI Design during the program.
Dr RS Gamad, head of Electronics and Instrumentation Engineering department, discussed ‘Research objective and challenges in Mixed Signal and RF VLSI Design’.
This lecture is very beneficial for new researcher because lecture include the proper steps to follow for research.
“Research process contains a series of closely related activities which has to carry out by a researcher,” Gamad said.
He explained research proposal writing, where one needs focus and patience. After explaining basics of mixed signal and radio frequency (RF), Gamad said, “RF electronics different from normal electronics because the at higher frequency signal easily radiate from the circuit and within the circuit and stray capacitance, skin effects also come into picture.”
Dr. Vaibhav Neema from IET DAVV discussed ‘VLSI design Techniques for low power Application’. “Space, power consumption and speed are major design issues in VLSI circuit,” he said.
He added that power reduction technique is emerging area of research in VLSI. Neema explained various techniques for leakage current reduction.