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Updated on: Monday, August 16, 2021, 04:53 PM IST

IIT Guwahati researchers make key breakthrough in memory chips

IIT-Guwahati researchers made fundamental contributions to memory architectures by preventing redundancy in data values and improving slow and frequent writes in the multi-core processor systems/ Representational image | pexels

IIT-Guwahati researchers made fundamental contributions to memory architectures by preventing redundancy in data values and improving slow and frequent writes in the multi-core processor systems/ Representational image | pexels

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A team of IIT-Guwahati researchers has made a key breakthrough in memory chips, making fundamental contributions to memory architectures by preventing redundancy in data values and improving slow and frequent writes in the multi-core processor systems.

The breakthrough will solve problems in multi-core processor-based systems that need an equally large on-chip memory to commensurate the data demands of the ever-growing applications, preventing energy consumption to ensure the temperature remains under the thermal design power (TDP) budget.

"The application data access patterns are not uniformly distributed and hence leads to several orders of writes to certain memory locations compared to others. Such heavily written locations become prone to wear-out and thus prevents the use of complete memory device without error corrections," said professor Hemangee K Kapoor, Department of CSE, IIT Guwahati.

Artificial Intelligence (AI) and Machine Learning (ML) are used as tools to solve several real-time problems.

"However, they involve enormous computations on huge datasets. Building close to memory accelerators to process the data are efficient in performance as well as energy," the research team said.

The findings of their research have been published in several reputed peer-reviewed journals.

"The team is also working on extending them to off-chip main memory. The future challenges are to handle lifetime enhancement in presence of encryption methods used to secure the Non-volatile memory and to handle temperature and process technology driven disturbance errors introduced when the cells are read or written," Kapoor added.

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Published on: Monday, August 16, 2021, 04:53 PM IST
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